MIPS

Microprocessor without Interlocked Pipelined Stages rappresenta una architettura di istruzioni (ISA) per computer a ridotto insieme di istruzioni (RISC), sviluppata da MIPS Computer Systems, oggi MIPS Technologies, negli Stati Uniti.

Esistono diverse versioni di MIPS, incluse le versioni storiche I, II, III, IV, e V. E parallelamente, cinque release di  MIPS32/64 (per implementazioni a 32- e 64-bit rispettivamente). Le prime architetture erano solo a 32-bit; le versioni a 64-bit furono sviluppate in seguito. Ad Aprile del 2017, la versione attuale era la MIPS32/64 Release 6. Le versioni 32/64 differiscono dalle versioni I–V principalmente nella definizione del privileged kernel mode System Control Coprocessor in aggiunta alla architettura user mode.

I corsi di Computer architecture nelle università e negli istituti tecnici studiano spesso questa architettura, in quanto questa ha influenzato le successive architetture RISC, come l’architettura Alpha.

MIPS logo

MIPS (Microprocessor without Interlocked Pipelined Stages) is a reduced instruction set computer (RISC) instruction set architecture (ISA) developed by MIPS Computer Systems, now MIPS Technologies, based in the United States.

There are multiple versions of MIPS: including version I, II, III, IV, and V; as well as five releases of MIPS32/64 (for 32- and 64-bit implementations, respectively). The early architectures were 32-bit only; 64-bit versions were developed later. As of April 2017, the current version is MIPS32/64 Release 6. Versions 32/64 primarily differs from versions I–V by defining the privileged kernel mode System Control Coprocessor in addition to the user mode architecture.

Computer architecture courses in universities and technical schools often study this architecture. The architecture greatly influenced later RISC architectures such as Alpha.